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Object-oriented modelling and performance evaluation of digital hardware architectures.
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Keywords: Object-oriented modelling, simulation, validation, performance evaluation, digital architectures.
Abstract: SEP is an incremental component-oriented method to evaluate performances of digital hardware architectures. Structural models are constructed using basic components, connectors and compositional rules. A discrete-event simulation environment allows the performance evaluation of the models relatively to some critical applications. The resulting model may be used as a reference to build VHDL or Verilog code.
Firstly, we have defined a generic model using UML (Unified Modelling Language). This model allows for an unified modelling of heterogeneous architectures and the definition of a computer-aided graphical environment independent of an architecture type. The behaviour of basic components is actively specified from Java methods. The component-oriented approach allows enhancement of readability and reusability, instruction-set modelling and integration of Esterel modules.
Secondly, we advocate the easiness to integrate some validation techniques into our simulation environment thanks to our model properties. In particular, a tool checks composition of components and high-level services. Moreover a dynamic binding mechanism replacing the Java one, efficiently takes care of specified types to perform functional validations.
Finally, in the last part we use our graphical environment to validate our method on industrial applications.


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