Laboratoire I3S - UMR7271

  h
France Deutch English Italiano Spanish
Se connecter

Réservation de salles - Salle 007 (salle de conférence - visioconf niv0 - Algorithmes)(70 personnes max.)
Semaine : lundi 29 mai - dimanche 04 juin

Heurelundi 29 mai mardi 30 mai mercredi 31 mai jeudi 01 juin vendredi 02 juin samedi 03 juin dimanche 04 juin
08:00 - 08:30
08:30 - 09:00
09:00 - 09:30
09:30 - 10:00
10:00 - 10:30 Logical Analysis of Distributed Systems: The Importance of Being Constructive
10:00 à 11:00Dans le cadre de l'appel AAPI2 - AIDE A LA MOBILITE LONGUE, le prof Michael Mendler, University of Bamberg (E-Mail: michael.mendler@uni-bamberg.de WWW: https://www.uni-bamberg.de/gdi/team/michael-mendler/), visitera l'I3S. A partir de jeudi 26 mai, le prof. Mendler sera ravi de rencontrer et échanger des chercheurs du Labo à leur convenance. En outre, le 2nd juin (vendredi) à 10h AM il donnera l'exposé : Titre Logical Analysis of Distributed Systems: The Importance of Being Constructive Abstract. The design and analysis of complex distributed systems proceeds along numerous levels of abstractions. One key abstraction step is the passage from analog transistor electronics to synchronously clocked sequential circuits. This significantly reduces the modelling complexity from continuous differential equations over the real numbers to discrete Mealy automata over two-valued Boolean algebra. Although typically taken for granted, this step is magic. How do we obtain clock synchronization from asynchronous communication of continuous values? How do we decide on the discrete meaning of continuous signals without a synchronization clock? From a logical perspective, the possibility of synchronization is paradoxical and appears “out of thin air.” This talk revisits the logical justification of the synchronous abstraction claiming that correctness arguments must intrinsically depend on reasoning in classical logic. The well-known result that some synchronization elements cannot be implemented in delay-insensitive circuits is related to “Berry’s Thesis” according to which digital circuits are delay-insensitive if and only if they are provably correct in constructive logic. More technically, the talk will show how non-inertial delays give rise to a constructive modal logic while inertial delays are inherently non-constructive. This gives a logical explanation for why inertial delays can be used to build arbiters, memory-cells and other synchronization elements, while non-inertial delays are not powerful enough. These results indicate the importance of logical constructiveness for metastable-free discrete abstractions of physical behavior. Local Contacts: L. Liquori and R. De Simone
10:30 - 11:00
11:00 - 11:30
11:30 - 12:00
12:00 - 12:30
12:30 - 13:00 Ecole Doctorale
12:30 à 17:30		 Team meeting Bioinfo
12:30 à 14:00
13:00 - 13:30
13:30 - 14:00 Répétition exposé projet SIS
13:30 à 15:30
14:00 - 14:30
14:30 - 15:00
15:00 - 15:30 Réunion Maquettes M1 - DS4H
15:00 à 18:00C. Di Giusto, E. Formenti, A. Tettamanzi
15:30 - 16:00
16:00 - 16:30
16:30 - 17:00
17:00 - 17:30
17:30 - 18:00
18:00 - 18:30
18:30 - 19:00
^ Haut de la page